HPCx Technology Phases 2 & 3

• Phase 2 (2004): 6 TFlop/s Rmax Linpack

  • ᡠ Regatta-H+ compute systems
    • 32 x 1.8GHz processors, 32 GB memory, full SMP mode (no LPAR)
  • 3 Regatta-H I/O systems (Double the capabilities of Phase 1)
  • "Federation" switch fabric
    • bandwidth quadrupled, ~5-10 microsecond latency, Connect to GX bus directly

• Phase 3 (2006): 12 TFlop/s Rmax Linpack

  • ᡠ Regatta-H+ compute systems
    • unchanged from Phase 2
  • ᡠ additional Regatta-H+ compute systems
    • double the existing configuration
  • 4 Regatta I/O systems (Double the capabilities of Phase 2)

• Open to Alternative Technology Solutions (IPF, BlueGene/L ..)

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